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16-pin soic integrated circuit systems, inc. ics1562b description the ics1562b is a very high performance monolithic phase- locked loop (pll) frequency synthesizer. utilizing ics?s ad- vanced cmos mixed-mode technology, the ics1562b provides a low cost solution for high-end video clock genera- tion. the ics1562b has differential video clock outputs (clk+ and clk-) that are compatible with industry standard video dac. another clock output, load, is provided whose frequency is derived from the main clock by a programmable divider. an additional clock output is available, ld/n2, which is derived from the load frequency and whose modulus may also be programmed. operating frequencies are fully programmable with direct con- trol provided for reference divider, prescaler, feedback divider and post-scaler. reset of the pipeline delay on brooktree ramdac ? s may be performed under register control. outputs may also be set to desired states to facilitate circuit board testing. user programmable differential output graphics clock generator features ? two programming options: ics1562b- 001 (parallel programming) ics1562b- 201 (serial programming) ? supports high-resolution graphics - clk output to 260 mhz, with 400 mhz options available ? eliminates need for multiple ecl output crystal oscillators ? fully programmable synthesizer capability - not just a clock multiplier ? circuitry included for reset of brooktree r amdac pipe- line delay ? vram shift clock generation capability (-201 option only) ? external feedback loop capability (-201 option only) ? compact - 16-pin 0.150? skinny soic package ? fully backward compatible to ics1562 crystal oscillator / r phase- frequency detector charge pump loop filter vco prescaler / a / m mux mux / 2 / 4 / n1 mux driver diff. output driver / n2 programming interface clk+ clk ? load ld/n2 xtal1 xtal2 ics1562b - 001 pinout ics1562b - 201 pinout simplified block diagram - ics1562b feedback divider extfbk blank ? ? ? (-201 only) figure 1 1562 b rev b 10/07/04 ramdac is a trademark of brooktree corporation. ad0 1 16 ad1 xtal1 2 15 ad2 xtal2 3 14 ad3 strobe 4 13 vdd vss 5 12 vddo vss 6 11 iprg load 7 10 clk+ ld/n2 8 9 clk- 16-pin soic extfbk 1 16 data xtal1 2 15 hold xtal2 3 14 blank datclk 4 13 vdd vss 5 12 vddo vss 6 11 iprg load 7 10 clk+ ld/n2 8 9 clk-
overview the ics1562b is ideally suited to provide the graphics system clock signals required by high-performance video dacs. fully programmable feedback and reference divider capability allow virtually any frequency to be generated, not just simple multiples of the reference frequency. the ics1562b uses the latest generation of frequency synthesis techniques developed by ics and is completely suitable for the most demanding video applications. pll synthesizer description - ratiometric mode the ics1562b generates its output frequencies using phase- locked loop techniques. the phase-locked loop (or pll) is a closed-loop feedback system that drives the output frequency to be ratiometrically related to the reference frequency pro- vided to the pll (see figure 1). the reference frequency is generated by an on-chip crystal oscillator or the reference frequency may be applied to the ics1562b from an external frequency source. the phase-frequency detector shown in the block diagram drives the voltage-controlled oscillator, or vco, to a frequency that will cause the two inputs to the phase-frequency detector to be matched in frequency and phase. this occurs when: f(xtal1) . feedback divider f( vco) : = reference divider this expression is exact; that is, the accuracy of the output frequency depends solely on the reference frequency provided to the part (assuming correctly programmed dividers). the vco gain is programmable, which permits the ics1562b to be optimized for best performance at all operating frequencies. the reference divider may be programmed for any modulus from 1 to 128 in steps of one. the feedback divider may be programmed for any modulus from 37 through 448 in steps of one. any even modulus from 448 through 896 can also be achieved by setting the ?double? bit which doubles the feedback divider modulus. the feedback divider makes use of a dual-modulus prescaler technique that allows the programmable counters to operate at low speed without sacrificing resolution. this is an improvement over conventional fixed prescaler architectures that typically im- pose a factor-of-four penalty (or larger) in this respect. table 1 permits the derivator of ?a? & ?m? converter program- ming directly from desired modulus. pll post-scaler a programmable post-scaler may be inserted between the vco and the clk+ and clk- outputs of the ics1562b . this is useful in generating lower frequencies, as the vco has been optimized for high-frequency operation. the post-scaler allows the selection of: vco frequency vco frequency divided by 2 vco frequency divided by 4 internal register bit (auxclk) value load clock divider the ics1562b has an additional programmable divider (re- ferred to in figure 1 as the n1 divider) that is used to generate the load clock frequency for the video dac. the modulus of this divider may be set to 3, 4, 5, 6, 8, 10, 12, 16 or 20 under register control. the design of this divider permits the output duty factor to be 50/50, even when an odd modulus is selected. the input frequency to this divider is the output of the pll post-scaler described above. additionally, this divider can be disabled under register control. di g ital inputs - ic s 1 5 62 b - 0 01 option the ad0-ad3 pins and the strobe pin are used to load all control registers of the ics1562b (-001 option). the ad0- ad3 and strobe pins are each equipped with a pull-up and will be at a logic high level when not connected. they may be driven with standard ttl or cmos logic families. the address of the register to be loaded is latched from the ad0-ad3 pins by a negative edge on the strobe pin. the data for that register is latched from the ad0-ad3 pins by a positive edge on the strobe pin. see figure 2 for a timing d i a g r a m . af t e r p ow e r -up, the i c s 1 562 b - 001 r e qu i r e s 32 r e g - ister writes for new programming to become effective. since only 13 registers are used at present, the programming system can perform 19 ?dummy? writes to address 13 or 14 to com- plete the sequence. i c s1 56 2 b 2
digital inputs - ics1562b - 201 option the programming of the ics1562b - 201 is performed serially by using the datclk, data, and hold~pins to load an internal shift register. data is shifted into the register on the rising edge of datclk. the logic value on the hold~pin is latched at the same time. when hold~ is low, the shift register may be loaded without disturbing the operation of the ics1562b . when high, the shift register outputs are transferred to the control registers, and the new programming information be- comes active. ordinarily, a high level should be placed on the hold~ pin when the last data bit is presented. see figure 3 for the programming sequence. an additional control pin on the ics1562b - 201 , blank can perform either of two functions. it may be used to disable the phase-frequency detector in line-locked applications. alterna- tively, the blank pin may be used as a synchronous enable for vram shift clock generation. see sections on line-locked operations and vram shift clock generation for details. output description the differential output drivers, clk+ and clk, are current- mode and are designed to drive resistive terminations in a complementary fashion. the outputs are current-sinking only, with the amount of sink current programmable via the iprg pin. the sink current, which is steered to either clk+or clk-, is four times the current supplied to the iprg pin. for most applications, a resistor from vddo to iprg will set the current to the necessary precision. additionally, minor adjustment to the duty factor can be achieved under register control. the load output is a high-current cmos type drive whose frequency is controlled by a programmable divider that may be selected for a modulus of 3, 4, 5, 6, 8, 10, 12, 16 or 20. it may also be suppressed under register control. the load output may be programmed to output the vco frequency divided by 2 (see aux_n1 description in register mapping section), inde- pendent of the differential output and n1 divider modulus. the ld/n2 output is high-current cmos type drive whose frequency is derived from the load output. the programma- ble modulus may range from 1 to 512 in steps of one. 5 4 2 1 3 data valid address valid ad0-ad3 strobe ics1562b - 001 register loading figure 2 8 67 datclk data hold data_1 data_2 data_56 ics1562b - 201 register loading figure 3 this allows the synthesizer to be completely programmed for the desired frequency before it is made active. once the part has been ?unlocked? by the 32 writes, programming becomes effective immediately. all registers identified in the data sheet (0-9, 11, 12 & 15) must be written upon initial programming. the programming registers are not initialized upon power-up, but the latched outputs of those registers are. the latch is made transparent after 32 register writes. if any register has not been written, the state upon power-up (random) will become effective. registers 13 & 14 physically do not exist. register 10 does exist, but is reserved for future expansion. to insure compatibility with possible future modifications to the database, ics recommends that all three unused locations be written with zero. ics1562b 3
pipeline delay reset function the ics1562b implements the clocking sequence required to reset the pipeline delay on brooktree ramdacs when the load output is programmed for a modulus of either 3, 4, 5, 6, 8 or 10. this sequence can be generated by setting the appropriate register bit (dacrst) to a logic 1 and then reset- ting to logic 0. when changing frequencies, it is advisable to allow 500 mi- croseconds after the new frequency is selected to activate the reset function. the output frequency of the synthesizer should be stable enough at that point for the video dac to correctly execute its reset sequence. see figure 4 for a diagram of the pipeline delay reset sequence. reference oscillator and crystal selection the ics1562b has circuitry on-board to implement a pierce oscillator with the addition of only one external component, a quartz crystal. pierce oscillators operate the crystal in anti- (also called parallel-) resonant mode. see the ac charac- teristics for the effective capacitive loading to specify when ordering crystals. series-resonant crystals may also be used with the ics1562b. be aware that the oscillation frequency will be slightly higher than the frequency that is stamped on the can (typically 0.025- 0.05%). as the entire operation of the phase-locked loop depends on having a stable reference frequency, we recommend that the crystal be mounted as closely as possible to the package. avoid routing digital signals or the ics1562b outputs underneath or near these traces. it is also desirable to ground the crystal can to the ground plane, if possible. if an external reference frequency source is to be used with the ics1562b. it is important that it be jitter-free. the rising and falling edges of that signal should be fast and free of noise for best results. the loop phase is locked to the falling edges of the xtal1 input signals if the refpol bit is set to logic 0. i nternal feedback the ics1562b supports load (n1) and n2 divider chains to act as the feedback divider for the pll. the n1 and n2 divider chains allow a much larger modulus to be achieved than the pll?s own feedback divider. additionally, the output of the n2 counter is accessible off-chip for perform- ing horizontal reset of the graphics system, where necessary. this mode is set under register control (altloop bit). the reference divider (r counter) will ordinarily be set to divide by 1 in this mode, and the reference input will be supplied to the xtal1 input. the output frequency of the synthesizer will then be: f (clk) : = f (xtal1) . n1 . n2. by using the phase-detector hardware disable mode, the pll can be made to free-run at the beginning of the vertical interval of the external video, and can be reactivated at its completion. ics1562b-001 the ics1562b-001 supports phase detector disable via a special control mode. when the pdrsten (phase detector reset enable) bit is set and the last address latched is 15 (0fh), a high level on ad3 will disable pll locking. ics1562b-201 the ics1562b-201 supports phase detector disable via the blank pin. when the pdrsten bit is set, a high level on the blank input will disable pll locking. pipeline delay reset timing strobe or datclk clk+ load 10 9 11 12 t clk figure 4 ics1562b 4
external feedback operation the ics1562b - 201 option also supports the inclusion of an external counter as the feedback divider of the pll. this mode is useful in graphic systems that must be ?genlocked? to external video sources. when the extfben bit is set to logic 1, the phase-frequency detector will use the extfbk pin as its feedback input. the loop phase will be locked to the rising edges of the signal applied to the extfbk input if the fbkpol bit is set to logic 0. vram shift clock generation the ics1562b - 201 option supports vram shift clock gen- eration and interruption. by programming the n2 counter to divide by 1, the ld/n2 output becomes a duplicate of the load output. when the scen bit is set, the ld/n2 output may be synchronously started and stopped via the blank pin. when blank is high, the ld/n2 will be free-running and in phase with load. when blank is taken low, the ld/n2 output is stopped at a low level. see figure 5 for a diagram of the sequence. note that this use of the blank pin precludes its use for phase comparator disable (see line-locked operation). power-on initialization the ics1562b has an internal power-on reset circuit that performs the following functions: 1) sets the multiplexer to pass the reference frequency to the clk+ and clk- outputs. 2) selects the modulus of the n1 divider (for the load clock) to be four. these functions should allow initialization of most graphics systems that cannot immediately provide for register program- ming upon system power-up. because the power-on reset circuit is on the vdd supply, and because that supply is filtered, care must be taken to allow the reset to de-assert before programming. a safe guideline is to allow 20 microseconds after the vdd supply reaches 4 volts. programming notes vco frequency range: use the post-divider to keep the vco frequency as high as possible within its operating range. divider range: for best results in normal situations (i.e, pixel clock generation for hi-res displays), keep the refer- ence divider modulus as short as possible (for a frequency at the output of the reference divider in the few hundred khz to several mhz range). if you need to go to a lower phase comparator reference frequency (usually required for increased frequency accuracy), that is acceptable, but jitter performance will suffer somewhat. vco gain programming: use the minimum gain which can reliably achieve the vco frequency desired, as shown on the following page: vram shift clock control blank load ld/n2 figure 5 ics1562b 5
figure 6 vco gain max frequency 4 120 mhz 5 200 mhz 6 260 mhz 7* *special application. contact factory for custom product above 260 mhz. phase detector gain: for most graphics applications and divider ranges, set p[1, 0] = 10 and set p[2] = 1. under some circumstances, setting the p[2] bit ?on? can reduce jitter. during 1562 operation at exact multiples of the crystal frequency, p[2] bit = 0 may provide the best jitter performance. board test support it is often desirable to statically control the levels of the output pins for circuit board test. the ics1562b supports this through a register programmable mode, auxen. when this mode is set, two register bits directly control the logic levels of the clk+/clk- pins and the load pin. this mode is activated when the s[0] and s[1] bits are both set to logic 1. see register mapping for details. power supplies and decoupling the ics1562b has two vss pins to reduce the effects of package inductance. both pins are connected to the same potential on the die (the ground bus). both of these pins should connect to the ground plane of the video board as close to the package as is possible. the ics1562b has a vddo pin which is the supply of +5 volt power to all output drivers. this pin should be connected to the power plane (or bus) using standard high-frequency decou- pling practice. that is, capacitors should have low series induc- tance and be mounted close to the ics1562b . the vdd pin is the power supply pin for the pll synthesizer circuitry and other lower current digital functions. we recom- mend that rc decoupling or zener regulation be provided for this pin (as shown in the recommended application circuitry). this will allow the pll to ?track? through power supply fluctuations without visible effects. see figure 6 for typical external circuitry. ics1562b 6
1ad0 ad1 16 2 xtal1 ad2 15 3 xtal2 ad3 14 4 strobe vdd 13 5 vss vddo 12 6vss iprg 11 7 load clk+ 10 8 ld/n2 clk- 9 + +5v to ramdac ics1562b - 001 typical interface 82 82 820 820 data bus
select logic 1 extfbk data 16 2xtal1 hold 15 3xtal2 blank14 4 datclk vdd 13 5 vss vddo 12 6 vss iprg 11 7load clk+ 10 8 ld/n2 clk- 9 + +5v +5v +5v to ramdac ics1562b - 201 typical interface graphics controller programming interface
82 82 820 820 0.1 f 0.1 f 22 f 0.1 f 510 10
0.1 f 22 f 0.1 f 510 +5v 0.1 f 10 +5v figure 7 b) a) i c s 1 5 6 2 b 7
register mapping - ics1562b - 001 (parallel programming option) note: it is not necessary to understand the function of these bits to use the ics1562b . pc software is avai lable from ics to automatically generate all register values based on requirements. contact factory for details. reg# bit(s) bit ref. description 0 0-3 r[0]..r[3] reference divider modulus control bits 1 0-2 r[4]..r[6] modulus = value + 1 1 3 refpol pll locks to the rising edge of xtal1 input when refpol=1 and to the falling edge of xtal1 when refpol=0. 2 0-3 a[0]..a[3] controls a counter. when set to zero, modulus=7. otherwise, modulus=7 for ?value? underflows of the prescaler, and modulus=6 thereafter until m counter underflows. 3 0-3 m[0]..m[3] m counter control bits 4 0-1 m[4]..m[5] modulus = value + 1 4 2 fbkpol external feedback polarity control bit. the pll will lock to the falling edge of extfbk when fbkpol=1 and to the rising edge of extfbk when fbkpol=0. 4 3 dblfreq doubles modulus of dual-modulus prescaler (from 6/7 to 12/14). 5 0-3 n1[0]..n1[3] sets n1 modulus according to this table. these bits are set to imple- ment a divide-by-four on power-up. n1[3] n1[2] n1[1] n1[0] ratio 00003 00014 00104 00115 01006 01018 01108 011110 1x0012 1x0116 1x1016 1x1120 x=don?t care ics1562b 8
reg# bit(s) bit ref. description 6 0-3 n2[0]..n2[3] sets the modulus of the n2 divider. 7 0-3 n2[4]..n2[7] the input of the n2 divider is the output of the n1 divider in all clock modes except auxen. 8 3 n2[8] 8 0-2 v[0]..v[1] sets the gain of the vco. 9 0-1 p[0]..p[1] sets the gain of the phase detector according to this table. 9 3 [p2] phase detector tuning bit. normally should be set to one. v[2] v[1] v[0] vco gain (mhz/volt) 100 30 101 45 110 60 111 80 p[1] p[0] gain (ua/radian) 00 0.05 01 0.15 10 0.5 11 1.5 10 1 loaden~ load clock divider enable (active low). when set to logic 1, the load and ld/n2 outputs will cease toggling. 10 2 skew- differential output duty factor adjust. 10 3 skew+ skew+ skew- 0 0 default 0 1 reduces t high by approximately 100 ps 1 0 increases t high by approximately 100 ps 1 1 do not use ics1562b 9
reg# bit(s) bit ref. description 11 0-1 s[0]..s[1] pll post-scaler/test mode select bits s[1] s[0] description 0 0 post-scaler=1. f(clk)=f(pll). the output of the n1 divider drives the load output which, in turn, drives the n2 divider. 0 1 post-scaler=2. f(clk)=f(pll)/2. the output of the n1 divider drives the load output which, in turn, drives the n2 divider. 1 0 post-scaler=4. f(clk)=f(pll)/4. the output of the n1 divider drives the load output which, in turn, drives the n2 divider. 1 1 auxen clock mode. the auxclk bit drives the differential outputs clk+ and clk- and the auxn1 bit drives the load output which, in turn, drives the n2 divider. 11 2 aux_clk when in the auxen clock mode, this bit controls the differential outputs. 11 3 aux_n1 when in the auxen clock mode, this bit controls the load output (and consequently the n2 output according to its programming). when not in the auxen clock mode, this bit, if set to one, will over- ride the n1 divider modulus and output the vco frequency divided by two [f(pll)/2] at the load output. 12 0 reserved must be set to zero. 12 1 jampll tristates phase detector outputs; resets phase detector logic, and resets r, a, m, and n2 counters. 12 2 dacrst set to zero for normal operation. when set to one, the clk+output is kept high and the clk- output is kept low. (all other device func- tions are unaffected.) when returned to zero, the clk+ and clk- outputs will resume toggling on a rising edge of the ld output (+/- 1 clk period). to initiate a ramdac reset sequence, simply write a one to this register bit followed by a zero. 12 3 selxtal when set to logic 1, passes the reference frequency to the post-scaler. 15 0 altloop controls substitution of n1 and n2 dividers into feedback loop of pll. when this bit is a logic 1, the n1 and n2 dividers are used. 15 3 pdrsten phase-detector reset enable control bit. when this bit is set, the ad3 pin becomes a transparent reset input to the phase detector. see "internal feedback operation" section for more details on the operation of this function. ics1562b 10
register mapping - ics1562b- 201 (serial programming option) note: it is not necessary to understand the function of these bits to use the ics1562b. pc software is avai lable from ics to automatically generate all register values based on requirements. contact factory for details. bit(s) bit ref. description 1-4 n1[0]..n1[3] sets n1 modulus according to this table. these bits are set to implement a divide-by-four on power-up. n1[3] n1[2] n1[1] n1[0] ratio 00003 00014 00104 00115 01006 01018 01108 011110 1x0 012 1x0 116 1x1 016 1x1 120 5 reserved must be set to zero. 6 jampll tristates phase detector outputs, resets phase detector logic, and resets r, a, m, and n2 counters. 7 dacrst set to zero for normal operations. when set to one, the clk+ output is kept high and the clk- output is kept low. (all other device functions are unaffected.) when returned to zero, the clk+ and clk- outputs will resume toggling on a rising edge of the ld output (+/ ? 1 clk period). to initiate a ramdac reset sequence, simply write a one to this register bit followed by a zero. 8 selxtal when set to logic 1, passes the reference frequency to the post-scaler. 9 altloop controls substitution of n1 and n2 dividers into feedback loop of pll. when this bit is a logic 1, the n1 and n2 dividers are used. 10 scen vram shift clock enable bit. when logic 1, the blank pin can be used to disable the ld/n2 output. 11 extfbken external pll feedback select. when logic 1, the extfbk pin is used for the phase-frequency detector feedback input. 12 pdrsten phase detector reset enable control bit. when this bit is set, a high level on the blank input will disable pll locking. see " internal feedback operation" section for more details on the operation of this function. ics1562b 11
bit(s) bit ref. description 13-14 s[0]..s[1] pll post-scaler/test mode select bits. s[1] s[0] description 0 0 post-scaler=1. f(clk)=f(pll). the output of the n1 divider drives the load output which, in turn, drives the n2 divider. 0 1 post-scaler=2. f(clk)=f(pll)/2. the output of the n1 divider drives the load output which, in turn, drives the n2 divider. 1 0 post-scaler=4. f(clk)=f(pll)/4. the output of the n1 divder drives the load output which, in turn, drives the n2 divider. 1 1 auxen clock mode. the auxclk bit drives the differential outputs clk+ and clk- and the auxn1 bit drives the load output which, in turn, drives the n2 divider. 15 aux_clk when in the auxen clock mode, this bit controls the differential outputs. 16 aux_n1 when in the auxen clock mode, this bit controls the n1 output (and consequently the n2 output according to its programming). when not in the auxen clock mode, this bit, if set to one, will override the n1 divider modulus and output the vco frequency divided by two [f(pll)/2] at the load output. 17-24 n2[0]..n2[7] sets the modulus of the n2 divider. the input of the n2 divider is the 28 n2[8] output of the n1 divider in all clock modes except auxen. 25-27 v[0]..v[2] sets the gain of vco according to this table. v[2] v[1] v[0] vco gain (mhz/volt) 100 30 101 45 110 60 111 80 29-30 p[0]..p[1] sets the gain of the phase detector according to this table. p[1] p[0] gain (ua/radian) 00 0.05 01 0.15 10 0.5 11 1.5 31 reserved set to zero. 32 p[2] phase detector tuning bit. should normally be set to one. ics1562b 12
bit(s) bit ref. description 33-38 m[0]..m[5] m counter control bits modulus = value +1 39 fbkpol external feedback polarity control bit. the pll will lock to the falling edge of extfbk when fbkpol=1 and to the rising edge of extfbk when fbkpol=0. 40 dblfreq doubles modulus of dual-modulus prescaler (from 6/7 to 12/14). 41-44 a[0]..a[3] controls a counter. when set to zero, modulus=7. otherwise, modulus=7 for ?value? underflows of the prescaler, and modulus=6 thereafter until m counter underflows. 45 reserved set to zero. 46 loaden~ load clock divider enable (active low). when set to logic 1, the load and ld/n2 outputs will cease toggling. 47 skew- differential output duty factor adjust. 48 skew+ 49-55 r[0]..r[6] reference divider modulus control bits modulus = value + 1 56 refpol pll locks to the rising edge of xtal1 input when refpol=1 and to the falling edge of xtal1 when refpol=0. skew+ skew- 0 0 default 0 1 reduces t high by approximately 100 ps 1 0 increases t high by approximately 100 ps 1 1 do not use ics1562b 13
table 1 - ?a? & ?m? divider programming feedback divider modulus table a[2]..a[0]- 001 010 011 100 101 110 111 000 m[5]..m[0] 000000 7 000001 13 14 000010 19 20 21 000011 25 26 27 28 000100 31 32 33 34 35 000101 37 38 39 40 41 42 000110 43 44 45 46 47 48 49 000111 49 50 51 52 53 54 55 56 001000 55 56 57 58 59 60 61 63 001001 61 62 63 64 65 66 67 70 001010 67 68 69 70 71 72 73 77 001011 73 74 75 76 77 78 79 84 001100 79 80 81 82 83 84 85 91 001101 85 86 87 88 89 90 91 98 001110 91 92 93 94 95 96 97 105 001111 97 98 99 100 101 102 103 112 010000 103 104 105 106 107 108 109 119 010001 109 110 111 112 113 114 115 126 010010 115 116 117 118 119 120 121 133 010011 121 122 123 124 125 126 127 140 010100 127 128 129 130 131 132 133 147 010101 133 134 135 136 137 138 139 154 010110 139 140 141 142 143 144 145 161 010111 145 146 147 148 149 150 151 168 011000 151 152 153 154 155 156 157 175 011001 157 158 159 160 161 162 163 182 011010 163 164 165 166 167 168 169 189 011011 169 170 171 172 173 174 175 196 011100 175 176 177 178 179 180 181 203 011101 181 182 183 184 185 186 187 210 011110 187 188 189 190 191 192 193 217 011111 193 194 195 196 197 198 199 224 a[2]..a[0]- 001 010 011 100 101 110 111 000 m[5]..m[0] 100000 199 200 201 202 203 204 205 231 100001 205 206 207 208 209 210 211 238 100010 211 212 213 214 215 216 217 245 100011 217 218 219 220 221 222 223 252 100100 223 224 225 226 227 228 229 259 100101 229 230 231 232 233 234 235 266 100110 235 236 237 238 239 240 241 273 100111 241 242 243 244 245 246 247 280 101000 247 248 249 250 251 252 253 287 101001 253 254 255 256 257 258 259 294 101010 259 260 261 262 263 264 265 301 101011 265 266 267 268 269 270 271 308 101100 271 272 273 274 275 276 277 315 101101 277 278 279 280 281 282 283 322 101110 283 284 285 286 287 288 289 329 101111 289 290 291 292 293 294 295 336 110000 295 296 297 298 299 300 301 343 110001 301 302 303 304 305 306 307 350 110010 307 308 309 310 311 312 313 357 110011 313 314 315 316 317 318 319 364 110100 319 320 321 322 323 324 325 371 110101 325 326 327 328 329 330 331 378 110110 331 332 333 334 335 336 337 385 110111 337 338 339 340 341 342 343 392 111000 343 344 345 346 347 348 349 399 111001 349 350 351 352 353 354 355 406 111010 355 356 357 358 359 360 361 413 111011 361 362 363 364 365 366 367 420 111100 367 368 369 370 371 372 373 427 111101 373 374 375 376 377 378 379 434 111110 379 380 381 382 383 384 385 441 111111 385 386 387 388 389 390 391 448 notes : to use this table, find the desired modulus in the table. follow the column up to find the a divider programming values. follow the row to the left to find the m divider programming. some feedback divisors can be achieved with two or three combinations of divider settings. any are acceptable for use. the formula for the effective feedback modulus is: n =[(m +1) . 6] +a except when a=0, then: n=(m +1) . 7 under all circumstances: a m ics1562b 14
pin descriptions - ics1562b - 001 pin# name description 10 clk+ clock out (non-inverted) 9clk clock out (inverted) 7 load load output. this output is normally at the clk frequency divided by n1. 2 xtal1 quartz crystal connection 1/external reference frequency input 3 xtal2 quartz crystal connection 2 1 ad0 address/data bit 0 (lsb) 16 ad1 address/data bit 1 15 ad2 address/data bit 2 14 ad3 address/data bit 3 (msb) 8 ld/n2 divided load output. see text. 4 strobe control for address/data latch 13 vdd pll system power (+5v. see application diagram.) 12 vddo output stage power (+5v) 11 iprg output stage current set 5,6 vss device ground. both pins must be connected to the same ground potential. pin descriptions - ics1562b - 201 pin# name description 10 clk+ clock out (non-inverted) 9clk clock out (inverted) 7 load load output. this output is normally at the clk frequency divided by n1. 2 xtal1 quartz crystal connection 1/external reference frequency input 3 xtal2 quartz crystal connection 2 4 datclk data clock (input) 16 data serial register data (input) 15 hold~ hold (input) 14 blank blanking (input). see text. 8 ld/n2 divided load output/shift clock. see text. 1 extfbk external feedback connection for pll (input). see text. 13 vdd pll system power (+5v. see application diagram.) 12 vddo output stage power (+5v) 11 iprg output stage current set 5,6 vss device ground. both pins must be connected. ics1562b 15
absolute maximum ratings vdd, vddo (measured to v ss ). . . . . . . . . . . . . . . . . . . . . . . 7.0 v digital inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ss -0.5 to v dd + 0.5 v digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ss -0.5 to v ddo + 0.5 v ambient operating temperature . . . . . . . . . . . . . . . . . . . . . . . -55 to 125 c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150 c junction temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 c soldering temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 c recommended operating conditions vdd, vddo (measured to v ss ). . . . . . . . . . . . . . . . . . . . . . . 4.75 to 5.25 v operating temperature (ambient) . . . . . . . . . . . . . . . . . . . . . 0 to 70 c dc characteristics ttl-compatible inputs 001 option - (ad0-ad3, strobe), 201 option - (datclk, data, hold, blank, extfbk) parameter symbol conditions min max units input high voltage v ih 2.0 v dd +0.5 v input low voltage v il v ss -0.5 0.8 v input high current i ih v ih =vdd - 10 ua input low current i il v il =0.0 - 200 ua input capacitance c in -8pf hysteresis (strobe/datclk) v hys v dd =5v .20 .60 v xtal1 input parameter symbol conditions min max units input high voltage v xh 3.75 v dd +0.5 v input low voltage v xl v ss -0.5 1.25 clk+, clk- outputs parameter symbol conditions min max units differential output voltage 0.6 - v load, ld/n2 outputs parameter symbol conditions min max units output high voltage (ioh = 4.0ma) 2.4 - v output low voltage (iol = 8.0ma) - 0.4 v ics1562b 16
ac characteristics symbol parameter min typ max units f vco vco frequency (see note 1) 40 260 mhz f xtal crystal frequency 5 20 mhz cpar crystal oscillator loading capacitance 2 0 pf f load load frequency 80 mhz t xhi xtal1 high time (when driven externally) 8 ns t xlo xtal1 low time (when driven externally) 8 ns t lock pll acquire time (to within 1%) 500 s i dd vdd supply current 15 t.b.d. ma i ddo vddo supply current (excluding clk+/ termination) 20 t.b.d. ma t high differential clock output duty cycle (see note 2) 45 55 % j clk differential clock output cumulative jitter (see note 3) <0.06 pixel digi t al inpu t s - ics1 5 62 b - 0 01 1 address setup time 10 ns 2 address hold time 10 ns 3 data setup time 10 ns 4 data hold time 10 ns 5 strobe pulse width (t hi or t lo )20 ns digi t al inpu t s - ics1 5 62 b - 2 01 6 data/hold~ setup time 10 ns 7 data/hold~ hold time 10 ns 8 datclk pulse width (t hi or t lo )20 ns pipeline delay reset 9 reset activation time 2*tclk ns 10 reset duration 4*tload ns 11 restart delay 2*tload ns 12 restart matching -1*tclk +1.5*tclk ns digital outputs 13 clk+/clk clock rate 260 mhz 14 load to ld/n2 skew (shift clock mode) -2 0 +2 ns note 1: use of the post-divider is required for frequencies lower than 40 mhz on clk+ & clk- outputs. use of the post-divider is recommended for output frequencies lower than 65 mhz. note 2: using load circuit of figure 6. duty cycle measured at zero crossings of difference voltage between clk+ and clk-. note 3: cumulative jitter is defined as the maximum error (in the domain) if any clk edge, at any point in time, compared with the equivalent edge generated by an ideal frequency source. ics laboratory testing indicates that the typical value shown above can be treated as a maximum jitter specification in virtually all applications. jitter performance can depend somewhat on circuit board layout, decoupling, and register programming. ics1562b 17
ics 1562 b application information output circuit considerations for the ics1562b output circuitry the dot clock signals clk and clk- are typically the highest frequency signals present in the workstation. to minimize problems with emi, crosstalk, and capacitive loading extra care should be taken in laying out this area of the pc board. the ics1562b is packaged in a 0.2?-wide 16-pin soic pack- age. this permits the clock generator, crystal, and related components to be laid out in an area the size of a postage stamp. the ics1562b should be placed as close as possible to the ramdac. the clk and clk- pins are running at vhf frequencies; one should minimize the length of pcb trace connecting them to the ramdac so that they don?t become radiators of rf energy. at the frequencies that the ics1562b is capable of, pc board traces may be long enough to be a significant portion of a wavelength of that frequency. pc traces for clk and clk- should be treated as transmission lines, not just interconnecting wires. these lines can take two forms: microstrip and stripline. a microstrip line is shown below: essentially, the microstrip is a copper trace on a pcb over a ground plane. typically, the dielectric is g10 glass epoxy. it differs from a standard pcb trace in that its width is calculated to have a characteristic impedance. to calculate the charac- teristic impedance of a microstrip line one must know the width and thickness of the trace, and the thickness and dielectric constant of the dielectric. for g10 glass epoxy, the dielectric constant (e r ) is about 5. propagation delay is strictly a function of dielectric constant. for g10 propagation, delay is calculated to be 1.77 ns/ft. stripline is the other form a pcb transmission line can take. a buried trace between ground planes (or between a power plane and a ground plane) is common in multi-layer boards. attempting to create a workstation design without the use of multi-layer boards would be adventurous to say the least, the issue would more likely be whether to place the interconnect on the surface or between layers. the between layer approach would work better from an emi standpoint, but would be more difficult to lay out. a stripline is shown below: using 1 oz. copper (0.0015? thick) and 0.040? thickness g10, a 0.010? trace will exhibit a characteristic impedance of 75 in a stripline configuration. typically, ramdacs require a v ih of v aa -1.0 volts as a guaranteed logical ?1? and a v il of v aa -1.6 as a guaranteed logical ?0.? worst case input capacitance is 10 pf. output circuitry for the ics1562b is shown in the following diagram. it consists of a 4/1 current mirror, and two open drain output fets along with inverting buffers to alternately enable each current-sinking driver. both clk and clk- outputs are connected to the respective clock and clock inputs of the ramdac with transmission lines and terminated in their equivalent impedances by the thevenin equivalent impedances of r1 and r2 or r1? and r2?. 18
the ics1562b is incapable of sourcing current, so v ih must be set by the ratios of these resistors for each of these lines. r1 and r2 are electrically in parallel from an ac standpoint because v dd is bypassed to ground through bypass-capacitor network c b . if we picked a target impedance of 75 for our transmission line impedance, a value of 91 for r1 and r1? and a value of 430 for r2 and r2? would yield a thevinin equivalent characteristic impedance of 75.1 and a v ih value of v aa -.873 volts, a margin of 0.127 volts. this may be adequate; however, at higher frequencies one must contend with the 10 pf input capacitance of the ramdac. values of 82 for r1 and r1? and 820 for r2 and r2? would give us a characteristic impedance of 74.5 and a v ih value of v aa -.45. with a .55 volt margin on v ih , this voltage level might be safer. to set a value for v il , we must determine a value for i prg that will cause the output fet?s to sink an appropriate current. we desire v il to be v aa -1.6 or greater. v aa -2 would seem to be a safe value. setting up a sink current of 25 milliamperes would guarantee this through our 82 pull-up resistors. as this is controlled by a 4/1 current mirror, 7 ma into i prg should set this current properly. a 510 resistor from v dd to i prg should work fine. resistors rt and rt? are shown as series terminating resistors at the ics1562b end of the transmission lines. these are not required for operation, but may be useful for meeting emi requirements. their intent is to interact with the input capaci- tance of the ramdac and the distributed capacitance of the transmission line to soften up rise and fall times and conse- quently cut some of the high-order harmonic content that is more likely to radiate rf energy. in actual usage they would most likely be 10 to 20 resistors or possibly ferrite beads. c b is shown as multiple capacitors. typically, a 22 f tantalum should be used with separate .1 f and 220pf capacitors placed as close to the pins as possible. this provides low series inductance capacitors right at the source of high frequency energy. r d is used to isolate the circuitry from external sources of noise. five to ten ohms should be adequate. great care must be used when evaluating high frequency circuits to achieve meaningful results. the 10 pf input capaci- tance and long ground lead of an ordinary scope probe will make any measurements made with it meaningless. a low capacitance fet probe with a ground connection directly connected to the shield at the tip will be required. a 1ghz bandwidth scope will be barely adequate, try to find a faster unit. ics1562b output circuitry ics1562b application information 19
16-pin skinny soic package package dimensions ordering information ics156 2 b m- 001 or ics1562 b m- 201 example: ics 1 5 6 2 b m -xxx pat t e r n num be r ( 3 d i g i t num be r f o r par t s w i t h ro m c ode p a t t e r ns ) package type m=soic device type prefix i c s = s tan d a r d ics 15 6 2 b 20

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